Language Breakdown
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I-Shaped Developer
I-shapedSpecialist — deep expertise in Verilog
Collaboration Network
Global Impact visualization
Repos
40
PRs
0
Growth
+18%
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Coding Streak
Contribution activity over the past year
kost-b
@kost-b
Anton Malakhov
@anton-malakhov
Stephen Cagle
@samedhi
Aliaksei Chapyzhenka
@drom
marsohod4you
@marsohod4you
Top Repositories
FPGA exercise for beginners
SystemVerilog language-oriented exercises
Verilog implementation of RISC-V: RV32IAC plus much of B. 32-bit or 16-bit bus.
CPU microarchitecture, step by step
Submission for Tiny Tapeout 8 - Verilog HDL Projects. An adder with a separate flow control for each argument and the result.
Verilog examples and other materials for seminars in Tomsk, Novosibirsk and Astana
The set of cleaned-up examples based on 2017 trainings in Kiev, Novosibirsk, Tomsk, Novosibirsk and Astana
Code examples for the event in Kiev
Open Source Impact
Contributions to external projects